In the fabrication of MOS transistors, ion implantation techniques have been widely utilized in the channel region to either facilitate processing or to improve the operating parameters of the transistor. For example, channel implants have been utilized to provide threshold voltage adjustment, to reduce punch-through between the source and drain and for forming a buried-channel device by incorporating within the surface region impurities of the type opposite to that of the substrate impurities.
In the buried channel MOSFET, the conducting channel is in the bulk semiconductor rather than at the Si--SiO.sub.2 interface as in a conventional MOSFET. The actual doping profile for the channel region typically has the peak centered in the channel region such that a metallurgical junction is formed beneath the surface of the substrate. Therefore, a surface depletion region is formed at the Si--SiO.sub.2 interface and a junction depletion region is formed about the metallurgical junction. The width of these two depletion regions depends upon the applied voltages. The gate of the transistor modulates the width of the surface depletion region.
A buried channel MOSFET can be fabricated as a normally-on or a normally-off device, depending on the surface doping and junction depth. In a normally-off device, the junction depletion region and the surface depletion region normally touch or overlap to pinch off the buried channel region. The voltage difference between the gate, the Fermi level of the channel region and the Fermi level of the underlying substrate are such that the channel region is depleted of carriers. The gate voltage is then operable to vary the surface depletion region to allow, for example, holes in the P-channel transistor to flow from the source to the drain.
One problem that occurs in buried channel MOSFETs is when the length of the channel region is reduced. As the drain and the source are brought closer together, the surface depletion region under control of the gate is no longer able to fully pinch off the channel region when the drain has a large voltage potential disposed thereon. This is due to the fact that the large potential on the drain of a buried channel transistor overcomes the pinch off of the surface depletion region, thus resulting in leakage through the buried channel.
As channel lengths decrease further in MOSFETs, other departures from long channel behavior may occur. These departures, the short channel effects, arise as a result of a two-dimensional distribution of high electric fields in the channel region. One approach to avoid the short channel effect is to maintain the long channel behavior by simply scaling down all dimensions and voltages of a long channel MOSFET, so that the internal electric fields are the same. Traditionally, this shrinking includes oxide thickness, channel length, channel width and junction depth. In addition, doping levels are increased by a predetermined scaling factor and all voltages are reduced by the same scaling factor, leading to a reduction of the junction depletion width by that factor. As a result, the subthreshold current remains essentially the same for the long channel device and the scaled down device. However, there are limitations to the amount of scaling that can be accomplished and, as such, reduction in the channel length with respect to buried channel devices still results in limitations with respect to leakage. In order to further reduce the channel length of the buried channel transistor, other techniques in addition to scaling will be required.